rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad848/ad849 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 high speed, low power monolithic op amp features 725 mhz gain bandwidth C ad849 175 mhz gain bandwidth C ad848 4.8 ma supply current 300 v/ m s slew rate 80 ns settling time to 0.1% for a 10 v step C ad849 differential gain: ad848 = 0.07%, ad849 = 0.08% differential phase: ad848 = 0.08 8 , ad849 = 0.04 8 drives capacitive loads dc performance 3 nv/ ? hz input voltage noise C ad849 85 v/mv open loop gain into a 1 k v load C ad849 1 mv max input offset voltage performance specified for 6 5 v and 6 15 v operation available in plastic, hermetic cerdip and small outline packages. chips and mil-std-883b parts available. available in tape and reel in accordance with eia-481a standard applications cable drivers 8- and 10-bit data acquisition systems video and r f amplification signal generators product description the ad848 and ad849 are high speed, low power monolithic operational amplifiers. the ad848 is internally compensated so that it is stable for closed loop gains of 5 or greater. the ad849 is fully decompensated and is stable at gains greater than 24. the ad848 and ad849 achieve their combination of fast ac and good dc performance by utilizing analog devices junction isolated complementary bipolar (cb) process. this process enables these op amps to achieve their high speed while only requiring 4.8 ma of current from the power supplies. the ad848 and ad849 are members of analog devices family of high speed op amps. this family includes, among others, the ad847 which is unity gain stable, with a gain bandwidth of 50 mhz. for more demanding applications, the ad840, ad841 and ad842 offer even greater precision and greater output current drive. the ad848 and ad849 have good dc performance. when operating with 5 v supplies, they offer open loop gains of 13 v/mv (ad848 with a 500 w load) and low input offset voltage of 1 mv maximum. common-mode rejection is a minimum of 92 db. output voltage swing is 3 v even into loads as low as 150 w . applications highlights 1. the high slew rate and fast settling time of the ad848 and ad849 make them ideal for video instrumentation circuitry, low noise pre-amps and line drivers. 2. in order to meet the needs of both video and data acquisition applications, the ad848 and ad849 are optimized and tested for 5 v and 15 v power supply operation. 3. both amplifiers offer full power bandwidth greater than 20 mhz (for 2 v p-p with 5 v supplies). 4. the ad848 and ad849 remain stable when driving any capacitive load. 5. laser wafer trimming reduces the input offset voltage to 1 mv maximum on all grades, thus eliminating the need for external offset nulling in many applications. 6. the ad848 is an enhanced replacement for the lm6164 series and can function as a pin-for-pin replacement for many high speed amplifiers such as the ha2520/2/5 and el2020 in applications where the gain is 5 or greater. connection diagrams plastic (n), small outline (r) and cerdip (q) packages 1 2 3 4 8 7 6 5 top view (not to scale) nc = no connect null nc output +v s null Cin +in Cv s ad848/49 20-terminal lcc pinout nc = no connect nc nc nc offset null nc v+ nc nc nc ?n nc nc +in nc nc nc nc v 14 18 16 17 15 19 20 3 1 2 78 4 6 5 13 12 9 11 10 top view (not to scale) ad848se/883b offset null output
rev. b C2C ad848/ad849Cspecifications ad848j ad848a/s model conditions v s min typ max min typ max units input offset voltage 1 5 v 0.2 1 0.2 1 mv 15 v 0.5 2.3 0.5 2.3 mv t min to t max 5 v 1.5 2 mv 15 v 3.0 3.5 mv offset drift 5 v, 15 v 7 7 m v/ c input bias current 5 v, 15 v 3.3 6.6 3.3 6.6/5 m a t min to t max 5 v, 15 v 7.2 7.5 m a input offset current 5 v, 15 v 50 300 50 300 na t min to t max 5 v, 15 v 400 400 na offset current drift 5 v, 15 v 0.3 0.3 na/ c open loop gain v o = 2.5 v 5v r load = 500 w 9 13 9 13 v/mv t min to t max 7 7/5 v/mv r load = 150 w 8 8 v/mv v out = 10 v 15 v r load = 1 k w 12 20 12 20 v/mv t min to t max 8 8/6 v/mv dynamic performance gain bandwidth a vcl 3 5 5 v 125 125 mhz 15 v 175 175 mhz full power bandwidth 2 v o = 2 v p-p, r l = 500 w 5 v 24 24 mhz v o = 20 v p-p, r l = 1 k w 15 v 4.7 4.7 mhz slew rate 5 v 200 200 v/ m s r load = 1 k w 15 v 225 300 225 300 v/ m s settling time to 0.1% C2.5 v to +2.5 v 5 v 65 65 ns 10 v step, a v = C4 15 v 100 100 ns phase margin c load = 10 pf 15 v r load = 1 k w 60 60 degrees differential gain f = 4.4 mhz 15 v 0.07 0.07 % differential phase f = 4.4 mhz 15 v 0.08 0.08 degree common-mode rejection v cm = 2.5 v 5 v 92 105 92 105 db v cm = 12 v 15 v 92 105 92 105 db t min to t max 88 88 db power supply rejection v s = 4.5 v to 18 v 85 98 85 98 db t min to t max 80 80 db input voltage noise f = 10 khz 15 v 5 5 nv/ ? hz input current noise f = 10 khz 15 v 1.5 1.5 pa/ ? hz input common-mode voltage range 5 v +4.3 +4.3 v C3.4 C3.4 v 15 v +14.3 +14.3 v C13.4 C13.4 v output voltage swing r load = 500 w 5 v 3.0 3.6 3.0 3.6 v r load = 150 w 5v 2.5 3 2.5 3 v r load = 50 w 5 v 1.4 1.4 v r load = 1 k w 15 v 12 12 v r load = 500 w 15 v 10 10 v short circuit current 15 v 32 32 ma input resistance 70 70 k w input capacitance 1.5 1.5 pf output resistance open loop 15 15 w power supply operating range 6 4.5 6 18 6 4.5 6 18 v quiescent current 5 v 4.8 6.0 4.8 6.0 ma t min to t max 7.4 7.4/8.3 ma 15 v 5.1 6.8 5.1 6.8 ma t min to t max 8.0 8.0/9.0 ma notes 1 input offset voltage specifications are guaranteed after 5 minutes at t a = +25 c. 2 full power bandwidth = slew rate/2 p v peak . refer to figure 1. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. all others are guaranteed but not necessarily tested. specifications subject to change without notice. (@ t a = +25 8 c, unless otherwise noted)
rev. b C3C ad849j ad849a/s model conditions v s min typ max min typ max units input offset voltage 1 5 v 0.3 1 0.1 0.75 mv 15 v 0.3 1 0.1 0.75 mv t min to t max 5 v 1.3 1.0 mv 15 v 1.3 1.0 mv offset drift 5 v, 15 v 2 2 m v/ c input bias current 5 v, 15 v 3.3 6.6 3.3 6.6/5 m a t min to t max 5 v, 15 v 7.2 7.5 m a input offset current 5 v, 15 v 50 300 50 300 na t min to t max 5 v, 15 v 400 400 na offset current drift 5 v, 15 v 0.3 0.3 na/ c open loop gain v o = 2.5 v 5v r load = 500 w 30 50 30 50 v/mv t min to t max 20 20/15 v/mv r load = 150 w 32 32 v/mv v out = 10 v 15 v r load = 1 k w 45 85 45 85 v/mv t min to t max 30 30/25 v/mv dynamic performance gain bandwidth a vcl 3 25 5 v 520 520 mhz 15 v 725 725 mhz full power bandwidth 2 v o = 2 v p-p, r l = 500 w 5 v 20 20 mhz v o = 20 v p-p, r l = 1 k w 15 v 4.7 4.7 mhz slew rate 5 v 200 200 v/ m s r load = 1 k w 15 v 225 300 225 300 v/ m s settling time to 0.1% C2.5 v to +2.5 v 5 v 65 65 ns 10 v step, a v = C24 15 v 80 80 ns phase margin c load = 10 pf 15 v r load = 1 k w 60 60 degrees differential gain f = 4.4 mhz 15 v 0.08 0.08 % differential phase f = 4.4 mhz 15 v 0.04 0.04 degrees common-mode rejection v cm = 2.5 v 5 v 100 115 100 115 db v cm = 12 v 15 v 100 115 100 115 db t min to t max 96 96 db power supply rejection v s = 4.5 v to 18 v 98 120 98 120 db t min to t max 94 94 db input voltage noise f = 10 khz 15 v 3 3 nv/ ? hz input current noise f = 10 khz 15 v 1.5 1.5 pa/ ? hz input common-mode voltage range 5 v +4.3 +4.3 v C3.4 C3.4 v 15 v +14.3 +14.3 v C13.4 C13.4 v output voltage swing r load = 500 w 5 v 3.0 3.6 3.0 3.6 v r load = 150 w 5v 2.5 3 2.5 3 v r load = 50 w 5 v 1.4 1.4 v r load = 1 k w 15 v 12 12 v r load = 500 w 15 v 10 10 v short circuit current 15 v 32 32 ma input resistance 25 25 k w input capacitance 1.5 1.5 pf output resistance open loop 15 15 w power supply operating range 6 4.5 6 18 6 4.5 6 18 v quiescent current 5 v 4.8 6.0 4.8 6.0 ma t min to t max 7.4 7.4/8.3 ma 15 v 5.1 6.8 5.1 6.8 ma t min to t max 8.0 8.0/9.0 ma notes 1 input offset voltage specifications are guaranteed after 5 minutes at t a = +25 c. 2 full power bandwidth = slew rate/2 p v peak . refer to figure 1. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. all others are guaranteed but not necessarily tested. specifications subject to change without notice. ad848/ad849
ad848/ad849 rev. b C4C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 watts small outline (r) . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 watts cerdip (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 watts lcc (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 watts input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 6 v storage temperature range (q) . . . . . . . . C65 c to +150 c (n, r) . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +175 c lead temperature range (soldering 60 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause per- manent damage to the device. this is a stress rating only, and functional opera- tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 lcc: q ja = 150 c/watt mini-dip package: q ja = 110 c/watt cerdip package: q ja = 110 c/watt small outline package: q ja = 155 c/watt. metalization photograph contact factory for latest dimensions. (ad848 and ad849 are identical except for the part number in the upper right.) dimensions shown in inches and (mm). ordering guide gain min max bandwidth stable offset voltage temperature package model mhz gain mv range C 8 c option 1 ad848jn 175 5 1 0 to +70 n-8 AD848JR 2 175 5 1 0 to +70 r-8 ad848jchips 175 5 1 0 to +70 die form ad848aq 175 5 1 C40 to +85 q-8 ad848sq 175 5 1 C55 to +125 q-8 ad848sq/883b 175 5 1 C55 to +125 q-8 ad848se/883b 175 5 1 C55 to +125 e-20a ad849jn 725 25 1 0 to +70 n-8 ad849jr 2 725 25 1 0 to +70 r-8 ad849aq 725 25 0.75 C40 to +85 q-8 ad849sq 725 25 0.75 C55 to +125 q-8 ad849sq/883b 725 25 0.75 C55 to +125 q-8 ad847j/a/s 50 1 1 see ad847 data sheet notes 1 e = lcc; n = plastic dip; q = cerdip; r = small outline ic (soic). 2 plastic soic (r) available in tape and reel. ad848 available in s grade chips. ad849 available in j and s grade chips.
ad848/ad849 rev. b C5C figure 1. ad848 inverting amplifier configuration figure 1a. ad848 large signal pulse response figure 1b. ad848 small signal pulse response offset nulling the input voltage of the ad848 and ad849 are very low for high speed op amps, but if additional nulling is required, the circuit shown in figure 3 can be used. for high performance circuits it is recommended that a resistor (r b in figures 1 and 2) be used to reduce bias current errors by matching the impedance at each input. the offset voltage error caused by the input currents is decreased by more than an order of magnitude. figure 2. ad849 inverting amplifier configuration figure 2a. ad849 large signal pulse response figure 2b. ad849 small signal pulse response figure 3. offset nulling
figure 4. quiescent current vs. supply voltage (ad848 and ad849) figure 7. open loop gain vs. load resistance (ad848) figure 10. quiescent current vs. temperature (ad848 and ad849) ad848/ad849Ctypical characteristics rev. b C6C (@ t a = +25 8 c and v s = 6 15 v, unless otherwise noted) figure 5. large signal frequency response (ad848 and ad849) figure 8. open loop gain vs. load resistance (ad849) figure 11. short circuit current limit vs. temperature (ad848 and ad849) figure 6. output voltage swing vs. load resistance (ad848 and ad849) figure 9. output swing and error vs. settling time (ad848) figure 12. input bias current vs. temperature (ad848 and ad849)
ad848/ad849 rev. b C7C figure 13. open loop gain and phase margin vs. frequency (ad848) figure 16. harmonic distortion vs. frequency (ad848) figure 19. power supply rejection vs. frequency (ad848) figure 14. open loop gain and phase margin vs. frequency (ad849) figure 17. harmonic distortion vs. frequency (ad849) figure 20. power supply rejection vs. frequency (ad849) figure 15. normalized gain band- width product vs. temperature (ad848 and ad849) figure 18. slew rate vs. temperature (ad848 and ad849) figure 21. common-mode rejection vs. frequency
ad848/ad849 rev. b C8C c1261bC5C9/90 printed in u.s.a. grounding and bypassing in designing practical circuits with the ad848 or ad849, the user must remember that whenever high frequencies are involved, some special precautions are in order. circuits must be built with short interconnect leads. a large ground plane should be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high frequency coupling. sockets should be avoided because the increased interlead capacitance can degrade bandwidth. feedback resistors should be of low enough value to assure that the time constant formed with the capacitances at the amplifier summing junction will not limit the amplifier performance. resistor values of less than 5 k w are recommended. if a larger resistor must be used, a small (< 10 pf) feedback capacitor in parallel with the feedback resistor, r f , may be used to compen- sate for the input capacitances and optimize the dynamic per- formance of the amplifier. power supply leads should be bypassed to ground as close as possible to the amplifier pins. 0.1 m f ceramic disc capacitors are recommended. video line driver the ad848 functions very well as a low cost, high speed line driver of either terminated or unterminated cables. figure 22 shows the ad848 driving a doubly terminated cable. the termination resistor, r t , (when equal to the characteristic impedance of the cable) minimizes reflections from the far end of the cable. while operating off 5 v supplies, the ad848 maintains a typical slew rate of 200 v/ m s, which means it can drive a 1 v, 24 mhz signal on the terminated cable. a back-termination resistor (r bt , also equal to the characteristic impedance of the cable) may be placed between the ad848 output and the cable in order to damp any reflected signals caused by a mismatch between r t and the cables characteristic impedance. this will result in a cleaner signal, although it requires that the op amp supply 2 v to the output in order to achieve a 1 v swing at the line. figure 22. video line driver 100pf load 1000pf load figure 23. ad848 driving a capacitive load ad848/ad849Capplications often termination is not used, either because signal integrity requirements are low or because too many high frequency signals returned to ground contaminate the ground plane. unterminated cables appear as capacitive loads. since the ad848 and ad849 are stable into any capacitive load, the op amp will not oscillate if the cable is not terminated; however pulse integrity will be degraded. figure 23 shows the ad848 driving both 100 pf and 1000 pf loads. low noise pre-amp the input voltage noise spectral densities of the ad848 and the ad849 are shown in figure 24. the low wideband noise and high gain bandwidths of these devices makes them well suited as pre-amps for high frequency systems. figure 24. input voltage noise spectral density input voltage noise will be the dominant source of noise at the output in most applications. other noise sources can be minimized by keeping resistor values as small as possible. outline dimensions dimensions shown in inches and (mm). cerdip (q) package mini-dip (n) package small outline (r) package
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